Created Oct 13, 2026 · Latest reported quarter, ended Jun 30, 2026 (Q2): ASML, ONTO, KLAC (its fiscal Q4), SK hynix · ended Jun 28, 2026 (fiscal Q4): LRCX · ended Jul 26, 2026 (fiscal Q3): AMAT · ended Sep 3, 2026 (fiscal Q4): MU. Prices are Oct 9 closes (as quoted in the note) and Oct 13 mid-morning (vendor).
You sent an Oct 12, 2026 RBC Capital Markets equipment note arguing that a quiet change inside AI memory could add roughly $30 billion of chip-equipment spending. This page does three jobs. It teaches enough about memory and chip fabs to follow the argument, it rebuilds the note's arithmetic from its own assumptions, and it checks the claims against filings and press reports. It does not endorse the ratings. ASML AMAT LRCX KLAC ONTO are the five equipment names; MU, SK hynix and Samsung are the memory customers; TSM is the foundry that would build the new part.
Every HBM (high-bandwidth memory) stack has a bottom layer, the base die. Through HBM3E it was a simple chip made on the memory maker's own DRAM process. From HBM4 it is a real logic chip made on a foundry process, and the next version (HBM4E) is expected to bring custom designs and more advanced nodes. RBC's claim is that if SK hynix and Micron move their base dies to leading-edge logic nodes (TSMC's 3nm class), the number of base dies is large enough to need 50–93 thousand wafers per month of extra advanced foundry capacity, which means about $30 billion of incremental wafer fab equipment (WFE), mostly in the second half of 2027 and in 2028. On that basis RBC sees double-digit WFE growth through 2028 and rates ASML, Applied Materials, Lam and Onto Outperform and KLA Sector Perform.
Three words carry most of the argument, so fix them now. WFE is the equipment that processes wafers inside a fab (lithography, deposition, etch, cleaning, inspection). WSPM is wafer starts per month, the standard way to size a fab's capacity. Node is the process generation (N3 and N2 are TSMC's 3nm and 2nm class). Each step is explained below.
| Name | RBC rating | RBC target | Multiple RBC applies to CY27E EPS | Price at note (Oct 9 close) | Price Oct 13, ~11 am ET | Target vs. note price | Target vs. Oct 13 | Multiple the note price implies on the same EPS (my arithmetic) |
|---|---|---|---|---|---|---|---|---|
| ASML | Outperform | $2,100 | 32x | $1,780.34 | $1,702.49 | +18% | +23% | about 27x |
| AMAT | Outperform | $600 | ~34x | $507.03 | $472.28 | +18% | +27% | about 29x |
| KLAC | Sector Perform | $180 | 30x | $195.57 | $185.01 | −8% | −3% | about 33x |
| ONTO | Outperform (initiated Oct 2) | $400 | ~34x | $294.53 | $266.79 | +36% | +50% | about 25x |
| LRCX | Outperform (reiterated) | Named in the thesis, but the note carries no price, target or valuation section for it. Vendor quote Oct 13: $299.25, 52-week high $438.50. | ||||||
Sources: the RBC note (ratings, targets, multiples, Oct 9 prices); stockanalysis.com quote pages, Oct 13, 2026 (prices are intraday and will have moved). The last column divides the note-date price by the EPS I back out of each target (target ÷ multiple: ASML about $65.6, AMAT about $17.7, KLAC $6.0, ONTO about $11.8). Because the target and the price use the same EPS, the whole gap between them is a change in the multiple RBC assumes, not an earnings upgrade. KLAC is the reverse: the target sits below the price, so RBC is assuming the multiple compresses.
Every computer faces the same trade-off: memory that is fast is small and expensive per bit, and memory that is large and cheap is slow. So systems stack several kinds, each placed where its speed or its price matters most. Two families run through everything below. Volatile memory loses its contents when the power goes off (SRAM, DRAM, HBM). Non-volatile memory keeps them (NAND flash, NOR flash, hard disks). The names that dominate this note, DRAM, HBM and NAND, are three different points on that ladder.
The memory ladder: speed and price per bit versus capacity
Speeds are order-of-magnitude textbook figures, not product specifications. Everything in the top two tiers is volatile; NAND and below keep their data.
| Type | What it is | Where it lives | Who makes it | Why it matters here |
|---|---|---|---|---|
| SRAM static RAM | Each bit is held by a small circuit of about six transistors. Very fast, no refreshing needed, but it takes a lot of chip area, so it is small and costly. | Inside processors and GPUs as cache | Not a separate industry. It is built into logic chips, so it is made by TSMC, Samsung Foundry and Intel along with the processor. | The speed layer you never buy separately. It is made on logic processes, which is part of why the logic-process base die can hold extra circuitry that a DRAM process cannot. |
| DRAM dynamic RAM | Each bit is one transistor plus a tiny capacitor holding charge. The charge leaks, so the chip must refresh every cell thousands of times a second, which is what “dynamic” means. Cheap and dense enough for gigabytes. | Memory modules in servers and PCs, chips soldered onto phone and graphics boards, and the stacks on AI accelerators (HBM) | Samsung, SK hynix, Micron; China's CXMT is growing | The product whose price swings drive the memory cycle. HBM is a DRAM variant, so HBM growth uses up DRAM wafer capacity. |
| NAND flash | Stores charge in cells that survive power loss. Reads are fast for storage but slow next to DRAM, and cells wear out after many rewrites. Capacity comes from stacking cells vertically in hundreds of layers (“3D NAND”). | SSDs, phones, USB drives, memory cards | Samsung, SK hynix (including Solidigm), Kioxia, Micron, SanDisk, YMTC (China) | Storage for training data, checkpoints and the files an AI server serves. It moves with its own price cycle, separate from DRAM. |
| NOR flash | An older, smaller flash type that can be read like ordinary memory, used for boot code and firmware. | Cars, routers, industrial gear | Winbond, Macronix, Infineon and others | Niche. Not part of this thesis. |
| Hard disks, tape | Mechanical or magnetic storage, the cheapest per bit. | Data-center bulk storage, archives | Seagate, Western Digital, tape makers | Not memory chips, so outside this note. |
These descriptions are standard background knowledge, not figures from a specific source; company lists name the main producers, not every one.
All four are DRAM at heart, the same capacitor-per-bit cell. They differ in how the chip is wired and packaged to the processor, which sets the bandwidth, the power use and the price.
| Variant | Used in | Interface design | Peak bandwidth, from the interface arithmetic | Trade-off |
|---|---|---|---|---|
| DDR5 | Servers, desktops, laptops (as DIMM modules) | Narrow (64 bits per module), fast per pin, runs over a motherboard | One DDR5-6400 module: 6.4 GT/s × 8 bytes = about 51 GB/s | Cheap, upgradable, high capacity per module |
| LPDDR5X | Phones, thin laptops, some AI CPUs | Low-power version, soldered close to the processor | Similar order to DDR5 per channel, at much lower power | Power efficiency over absolute speed |
| GDDR | Graphics cards, game consoles | Narrow but very fast per pin, chips around the GPU | A 32-bit GDDR7 chip at 32 Gbps per pin: about 128 GB/s, and a card uses many chips | Higher speed than DDR, higher power, board-routing limits |
| HBM | AI accelerators (NVIDIA, AMD, Google TPU and others) | Very wide (1,024 bits on HBM3E, 2,048 on HBM4), moderate speed per pin, stacked beside the processor on a silicon interposer | HBM3E stack: about 1,024 bits × roughly 9.6 Gbps = about 1.2 TB/s. HBM4: 2,048 bits × roughly 8 Gbps = about 2 TB/s | By far the most bandwidth and best power per bit, but costly, hard to make and package, and uses about three times the wafer supply per bit |
Bandwidth figures are peak values worked out from interface width times data rate (my arithmetic); real products and rated speeds differ by vendor and generation. The wafer-supply ratio is Micron's figure for HBM3E versus DDR5, as reported (see the sources).
The highway analogy. DDR and GDDR move data down a few very fast lanes over a long road (the motherboard). HBM builds a motorway with 1,000-plus slower lanes and puts the memory right next to the processor. For AI, where a chip waits on memory far more than it waits on arithmetic, the wide, short path is worth a high price.
Where each memory type sits in an AI server
Each step is faster and smaller than the last. The HBM capacity in this chain is what the note's per-accelerator figures (288 GB up to 1 TB) describe.
A last note on emerging types: MRAM, ReRAM, phase-change and similar memories have been promised for years as faster non-volatile alternatives, but none has displaced DRAM or NAND at scale. Intel's 3D XPoint (Optane) is the cautionary example: it was wound down in 2022. For this note and the equipment names around it, DRAM, HBM and NAND are what matter.
Two products, one economics. DRAM is the fast, volatile working memory next to a processor; NAND flash is the slower, non-volatile storage in SSDs. Both are close to commodities: a bit from one maker is a bit from another, so price is set by industry supply against demand. Three companies make most of the world's DRAM (Samsung, SK hynix, Micron), with China's CXMT growing from a small base. By SK hynix's own F-1 filing, citing IDC, it held about 29% of DRAM revenue in Q1 2026 and ranked second in DRAM.
Why it is cyclical. A new fab takes two or more years to build and fill, so supply responds to price with a long lag. When prices are high every producer expands; when the new capacity lands together, prices collapse. The most recent downturn is the clean example: Micron's revenue fell from $30.76 billion in fiscal 2022 to $15.54 billion in fiscal 2023, with a GAAP net loss of $5.83 billion, as DRAM average selling prices dropped in the high-40s percent. Three years later the same company reported fiscal 2026 revenue of $133.19 billion and GAAP net income of $84.97 billion (versus $37.38 billion of revenue in fiscal 2025). Memory profits are the most violent in the whole supply chain, and equipment makers feel it with a lag because memory makers cut or raise tool orders when they see prices move.
What HBM changes. HBM stacks 8 to 16 DRAM dies vertically, links them with through-silicon vias (TSVs, tiny vertical wires) and sits the stack beside an AI processor on the same package, giving far more bandwidth than ordinary memory modules. Three features matter to an investor:
Anatomy of an HBM stack and where the base die sits
Schematic, not to scale. One stack has one base die, however many core dies are on top of it. That distinction matters for the note's arithmetic below.
Where the money comes from. Chipmakers (TSMC, Samsung, SK hynix, Micron, Intel, plus Chinese fabs such as SMIC and CXMT) buy tools from a handful of equipment suppliers. SEMI splits equipment into three groups: WFE (wafer processing, mask/reticle and fab-facilities equipment), plus test and assembly & packaging. SEMI's July 14, 2026 mid-year forecast puts 2025 WFE at $116.9 billion and 2026 at $143.9 billion (+23.1%), inside total equipment sales of $165.9 billion for 2026, rising to $229.5 billion by 2028. SEMI attributed the upgrade to HBM-related DRAM and leading-edge logic.
What the tools do. A wafer is built in many repeated loops: lay down a thin film (deposition), print a pattern (lithography), carve it (etch), polish and clean, then measure and inspect for defects. Each leading-edge chip passes through this loop dozens of times. The suppliers in this note sit at different points of the loop:
Where the five equipment names sit in the chip-making loop
↑ The loop repeats dozens of times per wafer. After it, back-end steps cut the wafer, stack and bond dies (for HBM, TSVs and bonding) and test them. Back-end tools come from other firms (bonders from Besi, Hanmi, ASMPT; testers from Advantest, Teradyne), though AMAT, LRCX, KLAC and ONTO also sell into packaging. Simplified from company descriptions and my own background knowledge; Tokyo Electron, a large Japanese supplier of deposition, etch and cleaning, is not in the note.
Why per-wafer tool spending rises with each node. Smaller nodes need more patterning steps, more EUV exposures and more inspection per wafer. IBS (an industry consultancy; figures as reported in press, from a few years ago) estimated a 50,000-WSPM fab at about $20 billion for 3nm and $28 billion for 2nm, roughly $400,000 and $560,000 per monthly wafer start, with about 80% of a new fab's cost going to equipment (SemiAnalysis). Multiply that equipment share and you get roughly $320,000 (N3) to $450,000 (N2) of tools per wafer start. Keep that range in mind: RBC's assumption, $333,000 to $444,000 per WSPM, sits inside it.
What limits supply today. Two bottlenecks matter more than demand right now. First, cleanroom space: press reports say AMAT's CEO has argued that cleanroom space and tool throughput, not demand, limit growth, and a Taiwanese report says ASML, Lam and KLA warned the same. Second, tool lead times: ASML's CFO reportedly said low-NA EUV capacity is nearly fully booked for 2027, and ASML is planning to add roughly 30% capacity. Equipment makers book revenue when tools ship, so a space or lead-time delay moves revenue between quarters even if the order is safe.
For HBM3E the base die was made inside the memory fab on the memory process, which is cheap but limits speed and power efficiency. Moving it to a FinFET logic node cuts power, raises transistor speed and turns the base die into a customizable chiplet (custom HBM, where NVIDIA, Google, Broadcom customers or others put their own logic into the stack). The cost is a new bill: one report estimates TSMC-made HBM4 base dies could cost three to four times SK hynix's 1b core dies.
| Maker | HBM4 base die (now) | HBM4E base die (2027 on) | How firm |
|---|---|---|---|
| SK hynix | TSMC logic process, reported as 12nm-class, paired with 1b DRAM; it has said it adopts TSMC logic from HBM4 | Reported to be weighing TSMC 3nm (Chosun Daily, Mar 20, 2026) and, separately, Intel Foundry for part of the volume (Herald Business, Aug 2026; SK hynix said some of the reports were untrue) | The move to TSMC is company-confirmed; the nodes are press reports |
| Samsung | In-house 4nm foundry process, paired with 1c DRAM | Reported to keep in-house 4nm, with a dual-track offer that lets customers choose Samsung or TSMC; 2nm base die for HBM5 per a Samsung executive | Press reports plus one executive statement |
| Micron | Sources disagree: an internal CMOS base die in one, TSMC in another | Logic dies for standard and custom HBM4E expected to be made by TSMC | Least clear of the three |
| TSMC (the supplier) | 12nm-class logic die for SK hynix HBM4 | Custom HBM4E logic die reportedly on N3P | Late-2025 trade report |
Sources: TrendForce, Mar 20, 2026 (relaying Chosun Daily, ETNews, TechPowerUp); TrendForce, Aug 31, 2026 (relaying Herald Business, Business Post, S-Journal). Almost all HBM4E and HBM5 node detail is reported, not disclosed.
Two consequences. First, this equipment demand is in logic foundry fabs (mostly TSMC), not in the memory makers' own fabs, which are a separate and larger spending pool also driven by HBM. Second, the shift was already public: the TSMC 3nm story for SK hynix appeared in March, so what the note adds is the dollar sizing, not the news that the base die is moving.
The note's logic is a chain, each link multiplying the last. I rebuilt it from the assumptions in the note; my numbers reproduce its low and high cases to rounding.
The estimate chain, with where each link is weak or strong
Steps 1–2 set the volume, 3–4 convert it to wafers, 5–6 convert wafers to dollars, 7 sets the comparison. The widest uncertainty sits in the first two links, not the last four.
The high case has 212 million more base dies than the low case. Splitting that by accelerator family (my arithmetic from the note's inputs):
| Accelerator group | Low case: units × stacks | High case: units × stacks | Base dies added (M) | Share of the gap |
|---|---|---|---|---|
| NVIDIA GPUs | 8.8M × 8 | 10.0M × 16 | +90 | 42% |
| Other buyers (Microsoft, Meta, OpenAI, ByteDance, others) | 6.0M × 8 | 10.0M × 12 | +72 | 34% |
| Google TPU | 9.9M × 16 | 11.7M × 16 | +29 | 14% |
| AMD | 2.0M × 12 | 2.5M × 16 | +16 | 8% |
| AWS Trainium | 4.2M × 8 | 4.9M × 8 | +6 | 3% |
Two points come out of this. The “other buyers” bucket, the least specific line in the exhibit, supplies a third of the spread through a 150% volume growth assumption. And the table lists ByteDance in a volume line the note labels ex-China; I do not know how the note treats it, so I flag it rather than resolve it.
Holding RBC's other assumptions fixed (390 good dies per wafer, 80% foundry share and $20B per 45k WSPM for the high case; 70% and $15B for the low), here is what changes the total. These are my illustrations of how fragile the point estimate is, not forecasts.
| Case | Base dies (M) | Foundry WSPM (k) | Incremental WFE ($B) |
|---|---|---|---|
| RBC low case | 334 | 50 | 16.7 |
| RBC high case | 546 | 93 | 41.5 |
| High volumes, but NVIDIA stays at 8 stacks | 466 | 80 | 35.4 |
| High case, but “other buyers” at the low-case 6M × 8 | 474 | 81 | 36.0 |
| Both of the two changes above | 394 | 67 | 30.0 |
| High volumes with the low foundry share and tool cost (70%, $15B) | 546 | 82 | 27.2 |
The result is robust in one sense and not in another. Even with several high-case assumptions removed, the answer stays in the high-$20 billions, so a number of this size does not depend on any single input. But the final figure is still the product of five uncertain links, so a range of $17–42 billion is a better description than “$30 billion.”
Stack count, not stack height. It is easy to conflate two things here. A move from 16-high to 12-high stacks (reported for Rubin Ultra) reduces core dies per stack and the memory capacity per stack; it does not change base dies, because there is still one base die per stack. What would change base dies is fewer stacks per package (reports describe lower-memory Rubin Ultra versions, and a smaller two-die design instead of the announced four-die one). Nvidia has not confirmed any of this.
| Claim | What the note says | What I found | Verdict |
|---|---|---|---|
| Samsung base die on 4nm | Already transitioned for HBM4 | Multiple press reports (Chosun Daily, S-Journal) say in-house 4nm | consistent |
| SK hynix on trailing-edge foundry process | 12nm foundry process | Company said it moved to TSMC logic starting with HBM4; the 12nm-class node is press-reported | consistent |
| Micron makes base die in-house | In-house today | Sources disagree for HBM4; HBM4E expected at TSMC | mixed |
| Migration to advanced nodes is “underappreciated” | Headline claim | The node shift was in the press by March 2026. The WFE sizing is the note's own and is not from another source I found | partly: sizing is the new part |
| It will be “mostly incremental” WFE | Leading-edge capacity is already tight, so new tools are needed | SK hynix reportedly weighed Intel Foundry (Aug 2026), which has existing capacity; the note does not mention it. The note itself says freed 12nm capacity might offset a little | untested alternative |
| Samsung may use external foundry for NVIDIA custom HBM | Unconfirmed reports | Consistent with “dual-track” reports about Samsung opening to TSMC | consistent, unconfirmed |
| TSMC N3 plus N2 capacity of about 320k WSPM in 2027 (TrendForce) | Base die demand could exceed 20% of it in 2028 | I could not find the TrendForce source. Press estimates of about 180k N3 now and 90–140k N2 by end of 2026 make 320k plausible. The 50–93k figure is 16–29% of 320k, and it compares 2028 demand with 2027 capacity, which overstates the share if TSMC keeps adding capacity | plausible, overstated share |
| 2026 WFE of $168B | Baseline for the $30B comparison | SEMI (Jul 14, 2026): $143.9B; Lam's guide (late July): low $150 billions; a BofA view quoted in press: about $144B. SEMI's total equipment figure ($165.9B) is close to the note's figure, but I cannot say whether that is the reason | baseline is high |
| Rubin Ultra has 16 HBM stacks and 1 TB | Assumed in the high case | Announced at GTC 2026 per press; press reports since August describe 12-high or lower-memory versions and possibly a two-die design; no Nvidia confirmation | at risk |
| Cost of tools per wafer start | $15–20B per 45k WSPM | Matches IBS-derived N3/N2 equipment costs (about $320–450k per WSPM) | consistent |
| Cleanroom space is a constraint | Listed as a risk | Corroborated in press reports of AMAT, ASML, Lam and KLA commentary (secondary sources); Samsung, SK hynix and Micron are reported to be racing for cleanroom shells | corroborated (secondary) |
| China share of revenue | ASML 20% of systems; AMAT about 30%; KLA over 30% | ASML: about 20% of 2026 net sales (company, comparable). AMAT: 26% of Semiconductor Systems and services revenue in fiscal Q3, about 28% of total (reports). KLA: not checked | close; KLA unverified |
| Historical valuation anchors | AMAT 5-year average 18x, peers 43x; KLA 5-year average 21x | Not reproducible from public sources in this session | not verified |
Other quirks I noticed but did not try to explain: Lam is named in the Outperform reiteration but has no section in the note; the note's company list shows four names with prices; the exhibit labels the stacks row “number of HBM dies,” which only means stacks if read with the text.
The equipment case depends on memory makers having both the cash and the confidence to keep spending. Here is what they reported and guided.
| Item (as of) | Figure | Source |
|---|---|---|
| MU fiscal Q4 2026 (ended Sep 3, 2026) | Revenue $54.23B (vs. $11.32B a year earlier); non-GAAP gross margin 87.0%; GAAP operating income $43.75B; FY2026 net capex $27.37B | Micron 8-K, Sep 2026 |
| MU fiscal Q1 2027 guide | Revenue $61.5B ± $1.5B; non-GAAP gross margin about 86.25% | Micron 8-K |
| MU capex and outlook | Reported raised capex plan for fiscal 2027 (about $11.5B in fiscal Q1 and about $25B in the first half); most of the increase is for buildings; new front-end fabs come on in stages from mid-2027 to 2030; management expects supply tighter in fiscal 2027–2028 | Press reports of the call (secondary) |
| SK hynix Q2 2026 | Revenue about ₩79.3 trillion; operating profit about ₩60.5 trillion (about 76% margin), slightly below consensus; HBM4 mass shipments began in Q2 | Press and Quartr summary |
| SK hynix US listing (Jul 2026) | 177.9M ADRs at $149, about $26.5B raised, the largest US IPO by a foreign company | Press reports |
| DRAM and NAND contract prices, Q4 2026 (TrendForce, Sep 30) | Conventional DRAM expected up 10–15% on the quarter (15–20% with HBM), NAND up 15–20%; increases are slowing | Secondary report of the release |
| Hyperscaler capex, 2026 | About $725B across Alphabet, Amazon, Microsoft and Meta, up about 77%; 2027 modelled above $1 trillion by some brokers | Press compilations of company guidance |
| TSMC 2026 capex | Guided to $60–64B at the July call, up from $52–56B, with capex over the next three years described as significantly higher than the last three | Press report of the Q2 call |
Reading the cycle. Memory margins of 76–87% are far above anything in the industry's history, and the whole pattern of 2023 (price collapse, loss, tool-order cuts) began from a high-margin year. A study of this note should treat the memory makers' willingness to keep ordering tools as the load-bearing assumption, even though the note itself focuses on the foundry side. One reported counter-signal is that suppliers are already reconsidering whether further fab expansion makes sense if demand is becoming predictable, with the risk of overbuilding later.
| Company | Where it touches the base-die thesis | Latest quarter (as of) | RBC's stated risks |
|---|---|---|---|
| ASML fiscal year Dec | Lithography: the EUV scanners that print the finest layers. The most direct link to new N3/N2-class foundry capacity, and the tool in shortest supply. | Q2 2026 (reported Jul 15): net sales about €9.3B; net system sales split 51% logic and 49% memory; 2026 guide €43–45B, with advanced-logic system sales +25% and memory +75%; about 65 low-NA EUV and 130 immersion systems; China about 20% of sales | TSMC capex cuts; weaker China; cleanroom space |
| AMAT fiscal year ends late Oct | Deposition, etch, CMP, TSV and packaging tools; the broadest range, and DRAM is 26% of its semiconductor systems revenue. | Fiscal Q3 2026 (ended Jul 26): revenue $9.12B (+25%); non-GAAP EPS $3.50; China 26% of systems and services (about 28% of total); advanced packaging expected up more than 70% in 2026; export controls expected to cut about $600M from fiscal 2026 revenue; Q4 guide $9.75–10.75B | TSMC capex; export controls and local Chinese tool makers |
| LRCX fiscal year ends June | Etch and deposition (plus TSV tools); the note includes it in the Outperform list but gives no standalone valuation. | June 2026 quarter (reported Jul 29): revenue $6.72B (+30%); non-GAAP EPS $1.82; NAND revenue doubled sequentially; China 26% of revenue (down from 34%); 2026 WFE guided to the low $150 billions; Sep-quarter guide $8.1B ± $0.4B | Not given in the note |
| KLAC fiscal year ends June | Process control (inspection and measurement); leading-edge logic is its best end market, which is why this thesis should help it, but RBC cites low memory exposure and a five-year-high valuation for Sector Perform. | Fiscal Q4 2026 (ended Jun 30): revenue $3.66B; process control 89% of revenue; advanced packaging process control about $1.1B in 2026; Sep-quarter guide $4.0B ± $0.2B; 10-for-1 stock split took effect June 2026 | TSMC capex; export controls (China over 30% per RBC); cleanroom space |
| ONTO fiscal year Dec | Not a base-die story: its case rests on advanced packaging inspection (the Dragonfly systems), panel-level packaging and silicon photonics. It benefits from HBM only as packaging grows. | Q2 2026 (ended Jun 30): revenue $343.1M (+35%); GAAP EPS $1.21 vs. non-GAAP $1.93; backlog above $1B; more than $200M of Dragonfly orders from one OSAT, mostly for 2027; advanced packaging growth now guided to about 80% | Advanced packaging slowdown; competition from KLA and ASML; panel and silicon-photonics ramp delays |
Sources: ASML Q2 2026 call transcript; Applied Materials fiscal Q3 2026 release and call highlights; Lam 8-K; KLA fiscal Q4 release and split 8-K; Onto 8-K. Where I relied on a call summary rather than the filing, the figure is as reported there.
Onto's two P/E figures. The vendor shows a trailing P/E near 100x and a forward P/E near 26x. One sourced piece of the explanation: Onto's GAAP and non-GAAP earnings differ a lot. In the first half of 2026 GAAP diluted EPS was $1.88 against non-GAAP $3.35, and amortization of acquired intangibles more than doubled to $39.4M from $16.9M. I did not confirm which EPS basis the vendor uses for either figure, so treat the gap as flagged, not explained.
Three views of 2026 wafer fab equipment (WFE) spending, $ billions
Bars scaled to $180B. Definitions of WFE can differ between sources, and the note does not state its definition. The gap matters because RBC measures its $30B increment against its own baseline.
These are the questions that separate the names, framed as “what you would have to believe.” They are not a ranking and not advice.
This is a tangent: it does not count toward progress or the Coverage Ledger. It links forward to Module 0017 (Semiconductors & Equipment: MU, AMD, INTC, LRCX, AMAT), where Micron, Lam and Applied Materials will appear, and to Module 0016 (Mega-Cap Tech, NVDA) for the buyer of the HBM stacks. ASML, KLAC, ONTO, TSM and SK hynix are not in the current ROADMAP, so they appear here only. It also links to the earlier tangents on grid equipment (the data-center demand side) and quantum computing (the foundry link). A reusable pair of terms, WFE and WSPM, belongs in the sector glossary when Module 0017 is built.
Where to check next: SEMI's release page, KLA's earnings call for China, and the HBM sections of SK hynix's and Samsung's next earnings calls.